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3.3v, 8mb, nonvolatile sram with clock ds3065wp 19-5450; rev 0; 7/10 ordering information typical operating circuit general description the ds3065wp consists of a static ram, a nonvolatile (nv) controller, and a real-time clock (rtc). these com - ponents are packaged on a surface-mount substrate and require post-assembly attachment of a ds9034i- pcx+ battery cap. whenever v cc is applied to the module, it powers the clock and sram from the external power source, and allows the contents of the clock reg - isters or sram to be modified. when v cc is powered down or out of tolerance, the controller write protects the memory contents and powers the clock and sram from the battery. applications raid systems and servers/gamingpos terminals/fire alarms industrial controllers/plcs data-acquisition systems routers/switches features s reflowable, 34-pin powercap package s integrated rtc s unconditionally write protects the clock and sram when v cc is out of tolerance s automatically switches to battery supply when v cc power failures occur s extended industrial temperature range (-40 n c to +85 n c) s underwriters laboratories recognized ce data address a0?a19 dq0?dq7 ce 20 bits 8 bits microprocessor or dsp 1024k x 8 nv sram and rtc wr we rd oe cs cs ds3065wp part temp range speed (ns) supply voltage (v) pin-package DS3065WP-100IND+ -40 n c to +85 n c 100 3.3 q 0.3 34 powercap module for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrated?s website at www.maximintegrated.com. downloaded from: http:///
2 maxim integrated 3.3v, 8mb, nonvolatile sram with clock ds3065wp stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on any pin relative to ground .... -0.3v to +4.6v operating temperature range .......................... -40 n c to +85 n c storage temperature range ............................ -55 n c to +125 n c lead temperature (soldering, 10s) ................................ +260 n c (intended for minor rework/touchup purposes only)soldering temperature (reflow) ...................................... +260 n c recommended operating conditions(t a = -40 n c to +85 n c, unless otherwise noted.) (note 1) dc electrical characteristics(v cc = 3.3v q 0.3v, t a = -40 n c to +85 n c, unless otherwise noted.) pin capacitance(t a = +25 n c, unless otherwise noted.) ac electrical characteristics(v cc = 3.3v q 0.3v, t a = -40 n c to +85 n c, unless otherwise noted.) absolute maximum ratings parameter symbol conditions min typ max units supply voltage v cc 3.0 3.3 3.6 v logic 1 input v ih 2.2 v cc v logic 0 input v il 0.0 0.4 v parameter symbol conditions min typ max units input leakage current i il -1.0 +1.0 f a i/o leakage current i io v ce = v cs = v cc -1.0 +1.0 f a output-current high i oh v oh = 2.4v -1.0 ma output-current low i ol v ol = 0.4v 2.0 ma standby current i ccs1 v ce = v cs = 2.2v 0.6 2.0 ma i ccs2 v ce = v cs = v cc - 0.2v 0.6 1.5 operating current i cco1 t rc = 200ns, outputs open 50 ma write-protection voltage v tp 2.8 2.9 3.0 v parameter symbol conditions min typ max units input capacitance c in not production tested 15 pf input/output capacitance c out not production tested 15 pf parameter symbol conditions min typ max units read cycle time t rc 100 ns access time t acc 100 ns oe to output valid t oe 50 ns rtc oe to output valid t oec 60 ns ce or cs to output valid t co 100 ns oe or ce or cs to output active t coe (note 2) 5 ns downloaded from: http:///
3 maxim integrated 3.3v, 8mb, nonvolatile sram with clock ds3065wp ac electrical characteristics (continued)(v cc = 3.3v q 0.3v, t a = -40 n c to +85 n c, unless otherwise noted.) power-down/power-up timing(t a = -40 n c to +85 n c, unless otherwise noted.) data retention(t a = +25 n c, unless otherwise noted.) ac test conditionsvoltage range on any pin relative to ground: -0.3v to +4.6v input pulse levels: v il = 0v, v ih = 2.7v input pulse rise and fall times: 5nsinput and output timing reference level: 1.5v output load: 1 ttl gate + c l (100pf) including scope and jig parameter symbol conditions min typ max units output high impedance from deselection t od (note 2) 40 ns output hold from address t oh 5 ns write cycle time t wc 100 ns write pulse width t wp (note 3) 75 ns address setup time t aw 0 ns write recovery time t wr1 (note 4) 5 ns t wr2 (note 5) 20 output high impedance from we t odw (note 2) 40 ns output active from we t oew (note 2) 5 ns data setup time t ds (note 6) 40 ns data hold time t dh1 (note 4) 0 ns t dh2 (note 5) 20 chip-to-chip setup time t ccs 40 ns parameter symbol conditions min typ max units v cc fail detect to ce , cs , and we inactive time t pd (note 7) 1.5 f s v cc slew from v tp to 0v t f 150 f s v cc slew from 0v to v tp t r 150 f s v cc valid to ce , cs , and we inactive t pu 2 ms v cc valid to end of write protection t rec 125 ms parameter symbol conditions min typ max units expected data-retention time t dr (notes 7, 8) 10 years downloaded from: http:///
4 maxim integrated 3.3v, 8mb, nonvolatile sram with clock ds3065wp read cycle write cycle 1 output data valid t rc t acc t co t oe t oec t oh t od t od t coe t coe v ih v ih v il v oh v ol v oh v ol v il v ih addresses ce orcs oe dout (see note 9.) v ih v ih v ih v ih v il v il v il data in stable addresses we dout din t wc v ih v ih v ih v ih v il v il v il highimpedance v ih v ih v il v il v ih v il v il v il v il t aw t wp t oew t dh1 t ds t odw t wr1 (see notes 2, 3, 4, 6, 10?13.) ce orcs downloaded from: http:///
5 maxim integrated 3.3v, 8mb, nonvolatile sram with clock ds3065wp write cycle 2 power-down/power-up condition t wc t aw t dh2 t ds t coe t odw t wp t wr2 v ih v il v ih addresses we dout din v il v ih v il v ih v il v il v il v il v ih v ih v il v ih data in stable v il v ih v il (see notes 2, 3, 5, 6, 10?13.) ce orcs t dr t pu t f t pd slews with v cc t r v ih t rec v cc v tp ~ 2.5v ce, we backup current supplied from lithium battery (see notes 1, 7.) and cs downloaded from: http:///
6 maxim integrated 3.3v, 8mb, nonvolatile sram with clock ds3065wp note 1: all voltages are referenced to ground. note 2: these parameters are sampled with a 5pf load and are not 100% tested. note 3: t wp is specified as the logical and of ce with we for sram writes, or cs with we for rtc writes. t wp is measured from the later of the two related edges going low to the earlier of the two related edges going high. note 4: t wr1 and t dh1 are measured from we going high. note 5: t wr2 and t dh2 are measured from ce going high for sram writes or cs going high for rtc writes. note 6: t ds is measured from the earlier of ce or we going high for sram writes, or from the earlier of cs or we going high for rtc writes. note 7: in a power-down condition, the voltage on any pin cannot exceed the voltage on v cc . note 8: the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is first applied by the user. minimum expected data-retention time is based upon a single convection reflow exposure, followed by an attachment of a new ds9034i-pcx+. this parameter is assured by component selection, process control, and design. it is not measured directly during production testing. note 9: we is high for any read cycle. note 10: v oe = v ih or v il . if v oe = v ih during write cycle, the output buffers remain in a high-impedance state. note 11: if the ce or cs low transition occurs simultaneously with or later than the we low transition, the output buffers remain in a high-impedance state during this period. note 12: if the ce or cs high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high-impedance state during this period. note 13: if we is low or the we low transition occurs prior to or simultaneously with the related ce or cs low transition, the output buffers remain in a high-impedance state during this period. downloaded from: http:///
7 maxim integrated 3.3v, 8mb, nonvolatile sram with clock ds3065wp typical operating characteristics (v cc = 3.3v, t a = +25 n c, unless otherwise noted.) rtc output-voltage low vs. output current ds3065wp toc06 output current (ma) output voltage (v) 4 3 2 1 0.1 0.2 0.3 0.4 0 05 v cc = +3.0v, t a = +25c rtc output-voltage high vs. output current ds3065wp toc05 output current (ma) output voltage (v) -1 -2 -3 -4 1.5 2.0 2.5 3.0 3.5 4.01.0 -5 0 v cc = +3.0v, t a = +25c sram output-voltage low vs. output current ds3065wp toc04 output current (ma) output voltage (v) 4 3 2 1 0.1 0.2 0.3 0.4 0 05 v cc = +3.0v, t a = +25c sram output-voltage high vs. output current ds3065wp toc03 output current (ma) output voltage (v) -1 -2 -3 -4 1.5 2.0 2.5 3.0 3.5 4.01.0 -5 0 v cc = +3.0v, t a = +25c power-supply current vs. power-supply voltage ds3065wp toc02 supply voltage (v) supply current (a) 3.4 3.2 400 500 600 700 800300 3.0 3.6 v ce = v cs = v cc t a = +25c power-supply current vs. power-supply voltage ds3065wp toc01 supply voltage (v) supply current (ma) 3.5 3.4 3.1 3.2 3.3 1 2 3 4 5 6 7 80 3.0 3.6 5mhz ce-activated50% duty cycle 1mhz ce-activated50% duty cycle 5mhz address-activated100% duty cycle 1mhz address-activated100% duty cycle downloaded from: http:///
8 maxim integrated 3.3v, 8mb, nonvolatile sram with clock ds3065wp pin configuration pin description powercap module top view a19 + a15a16 cs v cc we oece dq7dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd x2 x1 gnd bat a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a17 a18 ds3065wp 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 pin name function 1 a19 address input 19 2 a15 address input 15 3 a16 address input 16 4 cs active-low rtc chip-select input 5 v cc supply voltage 6 we active-low write-enable input 7 oe active-low output-enable input 8 ce active-low sram chip-enable input 9 dq7 data input/output 7 10 dq6 data input/output 6 11 dq5 data input/output 5 12 dq4 data input/output 4 13 dq3 data input/output 3 14 dq2 data input/output 2 15 dq1 data input/output 1 16 dq0 data input/output 0 17 gnd ground pin name function 18 a0 address input 0 19 a1 address input 1 20 a2 address input 2 21 a3 address input 3 22 a4 address input 4 23 a5 address input 5 24 a6 address input 6 25 a7 address input 7 26 a8 address input 8 27 a9 address input 9 28 a10 address input 10 29 a11 address input 11 30 a12 address input 12 31 a13 address input 13 32 a14 address input 14 33 a17 address input 17 34 a18 address input 18 downloaded from: http:///
9 maxim integrated 3.3v, 8mb, nonvolatile sram with clock ds3065wp functional diagram current-limiting resistor battery protection circuitry (ul recognized) redundant logic delay timing circuitry v tp ref v sw ref gnd ce ce redundant series fet sram dq0?dq7 oe we v cc v cc uninterrupted power supply for the sram and rtc oe we a0?a19 a0?a3 real-time clock we oe cs cs 32.768khz ds3065wp ds9034i-pcx+ downloaded from: http:///
10 maxim integrated 3.3v, 8mb, nonvolatile sram with clock ds3065wp detailed description the ds3065wp is an 8mb (1024k x 8 bits), fully static, nonvolatile (nv) memory similar in function and organiza - tion to the ds1265w nv sram, but containing an rtc. the device nv sram constantly monitors v cc for an out- of-tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. there is no limit to the number of write cycles that can be executed, and no additional support circuitry is required for microprocessor interfacing. this device can be used in place of sram, eeprom, or flash components. user access to either the sram or the rtc registers is accomplished with a byte-wide interface and discrete control inputs, allowing for a direct interface to many 3.3v microprocessor devices. the rtc contains a full-function clock/calendar with an rtc alarm, battery monitor, and power monitor. rtc registers contain century, year, month, date, day, hours, minutes, and seconds data in a 24-hour bcd format. corrections for day of the month and leap year are made automatically. the rtc registers are double-buffered into an internal and external set. the user has direct access to the exter - nal set. clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static data. assuming the internal oscillator is on, the internal registers are continually updated, regard - less of the state of the external registers, assuring that accurate rtc information is always maintained. the device constantly monitors the voltage of the internal battery. the battery-low flag (blf) in the rtc flags register is not writable and should always be a 0 when read. should a 1 ever be present, the battery voltage is below ~ 2v and the contents of the clock and sram are questionable. the device module is constructed on a standard 34-pin powercap substrate. sram read mode the device executes an sram read cycle whenever cs (rtc chip select) and we (write enable) are inactive (high) and ce (sram chip enable) is active (low). the unique address specified by the 20 address inputs (a0?a19) defines which of the 1,048,576 bytes of sram data is to be accessed. valid data is available to the eight data-output drivers within t acc (access time) after the last address input signal is stable, provided that ce and oe (output enable) access times are also satisfied. if ce and oe access times are not satisfied, data access must be measured from the later occurring signal ( ce or oe ), and the limiting parameter is either t co for ce or t oe for oe rather than address access. sram write mode the device executes an sram write cycle whenever cs is inactive (high) and the ce and we signals are active (low) after address inputs are stable. the later-occurring falling edge of ce or we determines the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the cs and oe control signal should be kept inactive (high) during sram write cycles to avoid bus contention. however, if the output drivers have been enabled ( ce and oe active), we disables the outputs in t odw from its falling edge. table 1. rtc/memory operational truth tablex = don?t care. cs we ce oe mode icc outputs 0 1 1 0 rtc read active active 0 1 1 1 rtc read active high impedance 0 0 1 x rtc write active high impedance 1 1 0 0 sram read active active 1 1 0 1 sram read active high impedance 1 0 0 x sram write active high impedance 1 x 1 x standby standby high impedance 0 x 0 x invalid (see figure 2) active invalid downloaded from: http:///
11 maxim integrated 3.3v, 8mb, nonvolatile sram with clock ds3065wp clock operations rtc read mode the device executes an rtc read cycle whenever ce (sram chip enable) and we (write enable) are inactive (high) and cs (rtc chip select) is active (low). the least significant four address inputs (a0?a3) define which of the 16 rtc registers is to be accessed (see table 3). valid data is available to the eight data-output drivers within t acc (access time) after the last address input signal is stable, provided that cs and oe (output enable) access times are also satisfied. if cs and oe access times are not satisfied, data access must be measured from the later-occurring signal ( cs or oe ) and the limit - ing parameter is either t co for cs or t oec for oe rather than address access. rtc write mode the device executes an rtc write cycle whenever ce is inactive (high) and the cs and we signals are active (low) after address inputs are stable. the later-occurring falling edge of cs or we determines the start of the write cycle. the write cycle is terminated by the earlier rising edge of cs or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the ce and oe control signals should be kept inactive (high) during rtc write cycles to avoid bus contention. however, if the output drivers have been enabled ( cs and oe active), we disables the outputs in t odw from its falling edge. clock oscillator mode the oscillator can be turned off to minimize current drain from the battery. the osc bit is the msb of the seconds register (b7 of f9h). setting osc to 1 stops the oscillator; setting osc to 0 starts the oscillator. the initial state of osc is not guaranteed. when power is applied for the first time, the osc bit should be enabled. reading the clock when reading the rtc data, it is recommended to halt updates to the external set of double-buffered rtc reg - isters. this puts the external registers into a static state, allowing the data to be read without register values changing during the read process. normal updates to the internal registers continue while in this state. external updates are halted by writing a 1 to the read bit (r). as long as a 1 remains in the r bit, updating is inhibited. after a halt is issued, the registers reflect the rtc count (day, date, and time) that was current at the moment the halt command was issued. normal updates to the external set of registers resume within one second after the r bit is set to 0 for a minimum of 500 f s. the r bit must be 0 for a minimum of 500 f s to ensure the external registers have fully updated. setting the clock as with a clock read, it is also recommended to halt updates prior to setting new time values. setting the write bit (w) to 1 halts updates of the external rtc registers 8h?fh. after setting the w bit to 1, the rtc registers can be loaded with the desired count (day, date, and time) in bcd format. setting the w bit to 0 then transfers the values written to the internal registers and allows normal clock operation to resume. using the clock alarm the alarm settings and control for the device reside within rtc registers 2h?5h. the interrupts register (6h) contains two alarm-enable bits: alarm flag enable (ae) and alarm in backup-mode enable (abe). the alarm can be programmed to activate on a specific day of the month or repeat every day, hour, minute, or second. alarm mask bits am[4:1] control the alarm mode (table 2). configurations not listed in the table default to the once-per-second mode to notify the user of an incor - rect alarm setting. table 2. alarm mask bits am4 am3 am2 am1 alarm rate 1 1 1 1 once per second 1 1 1 0 when seconds match 1 1 0 0 when minutes and seconds match 1 0 0 0 when hours, minutes, and seconds match 0 0 0 0 when date, hours, minutes, and seconds match downloaded from: http:///
12 maxim integrated 3.3v, 8mb, nonvolatile sram with clock ds3065wp when the rtc register values match alarm register set - tings, the alarm flag (af) is set to 1.the ae and abe bits are reset to 0 during the power-up transition, but an alarm generated during power-up sets af to 1. therefore, the af bit can be read after system power-up to determine if an alarm was generated during the power-up sequence. figure 1 illustrates alarm timing during battery-backup mode and power-up states. clock accuracy the ds3065wp and ds9034i-pcx+ are each individually tested for accuracy. once mounted together, the module typically keeps time accuracy to within q 1.53 minutes per month (35ppm) at +25 n c and does not require additional calibration. for this reason, methods of field clock calibration are not available and not necessary. the electrical environment also affects clock accuracy, and caution should be taken to place the component in the lowest level emi section of the pcb layout. for addi - tional information, refer to application note 58: crystal considerations with dallas real-time clocks (rtcs) . power-on default states upon each application of power to the device, the fol - lowing register bits are automatically set to 0: wds = 0, bmb[4:0] = 0, rb0 = 0, rb1 = 0, ae = 0, abe = 0. all other rtc bits are undefined. data-retention mode the device provides full functional capability for v cc greater than 3.0v and write protects by 2.8v. data is maintained in the absence of v cc without additional sup - port circuitry. the nv sram constantly monitors v cc . should the supply voltage decay, the nv sram auto - matically write protects itself. all inputs become don?t care, and all data outputs become high impedance. as v cc falls below approximately 2.5v (v sw ), the power- switching circuit connects the lithium energy source to the clock and sram to maintain time and retain data. during power-up, when v cc rises above v sw , the pow - er-switching circuit connects external v cc to the clock and sram and disconnects the lithium energy source. normal clock or sram operation can resume after v cc exceeds v tp for a minimum duration of t rec . freshness seal when the ds9034i-pcx+ battery cap is first attached to a ds3065wp base, the rtc oscillator is disabled and the lithium battery is electrically disconnected, guaran - teeing that no battery capacity has been consumed dur - ing transit or storage.when v cc is first applied at a level greater than v tp , the lithium battery is enabled for backup operation. the user is required to enable the oscillator (msb of the seconds register) and initialize the required rtc reg - isters for proper timekeeping operation. figure 1. battery-backup mode alarm waveforms v cc v tp abe, ae af downloaded from: http:///
13 maxim integrated 3.3v, 8mb, nonvolatile sram with clock ds3065wp table 3. rtc register map addr data function range b7 b6 b5 b4 b3 b2 b1 b0 xxxxfh 10 year year year 00?99 xxxxeh x x x 10 mo month month 01?12 xxxxdh x x 10 date date date 01?31 xxxxch x ft x x x day day 01?07 xxxxbh x x 10 hour hour hour 00?23 xxxxah x 10 minutes minutes minutes 00?59 xxxx9h osc 10 seconds seconds seconds 00?59 xxxx8h w r 10 century century control 00?39 xxxx7h y y y y y y y y unused ? xxxx6h ae y abe y y y y y interrupts ? xxxx5h am4 y 10 date date alarm date 01?31 xxxx4h am3 y 10 hr hours alarm hours 00?23 xxxx3h am2 10 minutes minutes alarm minutes 00?59 xxxx2h am1 10 seconds seconds alarm seconds 00?59 xxxx1h y y y y y y y y unused ? xxxx0h wf af 0 blf 0 0 0 0 flags ? x = don?t care address bits r = read bit x = unused; read/writable under write and read bit control ae = alarm flag enable y = unused; read/writable without write and read bit control abe = alarm in backup-mode enable 0 = reads as 0 and cannot be changed am[4:1] = alarm mask bits ft = frequency test bit wf = watchdog flag osc = oscillator start/stop bit af = alarm flag w = write bit blf = battery-low flag downloaded from: http:///
14 maxim integrated 3.3v, 8mb, nonvolatile sram with clock ds3065wp applications information power-supply decoupling to achieve the best results when using the device, decouple the power supply with a 0.1 f f capacitor. use a high-quality, ceramic, surface-mount capacitor if possible. surface-mount components minimize lead inductance, which improves performance, and ceram - ic capacitors tend to have adequate high-frequency response for decoupling applications. avoiding data bus contention care should be taken to avoid simultaneous access of the sram and rtc devices (see figure 2). any chip- enable overlap violates t ccs and can result in invalid and unpredictable behavior. recommended cleaning procedures the device can be cleaned using aqueous-based clean - ing solutions. no special precautions are needed when cleaning boards containing a ds3065wp module, pro - vided that the cleaning and subsequent drying process is completed prior to the ds9034i-pcx+ attachment. ds3065w modules are recognized by underwriters laboratories (ul) under file e99151. package information for the latest package outline information and land patterns, go to www.maximintegrated.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. figure 2. sram/rtc data bus control t ccs t ccs ce v ih v ih v ih v ih cs package type package code outline no. land pattern no. 34 pcap ? 21-0246 see the outline no. 21-0246 downloaded from: http:///
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 15 ? 2010 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. 3.3v, 8mb, nonvolatile sram with clock ds3065wp revision history revision number revision date description pages changed 0 7/10 initial release ? downloaded from: http:///

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